1. Field of the Invention
The present invention relates to a clock phase corrector, and more specifically to a circuit for correcting the phase of a data sampling clock signal for use in sampling data included in a received packet carried by a demodulated signal.
2. Description of the Background Art
In radio communication systems, a receiver device is generally adapted to determine, on the basis of a synchronous signal or an inter-device identification included in the top field of a packet received, whether or not to take in, or sample, signals of the packet received. For example, some radio communications device has a radio receiver for receiving and demodulating a packet transmitted and over-sampling the top field of the packet with a clock signal having its rate several times as high as the data transfer rate. With such a radio communications device, data resultant from the over-sampling are compared with its inter-device identification to thereby detect the inter-device identification carried by the received packet. Further, on the basis of the timing at which the inter-device identification was detected, the radio communications device determines the phase of a data sampling clock signal for use in taking in, or sampling, data included in the received packet, and subsequently uses that data sampling clock signal having the phase thus determined to sample the data included in the received packet.
In the prior art, U.S. Pat. No. 6,618,459 to Tada issued on Sep. 9, 2003, discloses a radio communications device adapted, not to fix the phase of a clock signal for use in sampling received data, but to determine a difference in phase of a clock signal for sampling received data carried by a demodulated signal at each logical transition point of the data to adjust the phase of the clock signal adaptively to the difference thus determined.
However, the reference signals in a radio communications system involve a deviation and a fluctuation in frequency caused by its ambient temperature or aging to raise a difference in frequency of the reference signals between a transmitter and a receiver station. Even when a clock signal for sampling data is appropriately adjusted during the detection of an inter-device identification of a received signal, for example, the clock signal becomes gradually shifted in phase from the signals being received, as the time elapses, to the extent that data contained in a received packet near its end fail to be appropriately sampled, thus causing a possibility of losing the data. That was a difficulty in the prior art.
It could be possible to overcome that difficulty by utilizing a much higher frequency for over-sampling inter-device identification signals so as to define the timing for detecting inter-device identifications with extensive accuracy, thereby adjusting the phase of a clock signal for sampling received data to its most appropriate phase with higher accuracy. The increasing of the frequency of an over-sampling clock signal would result in an increased power consumption as well as a bar to miniaturization of the associated circuitry.
With the radio communications device disclosed in the U.S. patent to Tada stated above, the phase difference of a clock signal for sampling received data carried by a demodulated signal is determined at each of the transitions of the data values, and the phase of the clock signal is adaptively adjusted to the phase difference thus determined. That may indeed prevent a failure in sampling the received data due to deviation in phase. In order to correct the phase of a clock signal for sampling received data, however, circuitry is required for correcting the phase of the clock signal. Such phase corrector circuitry generally tends to be complicated in structure.